Verilog Code For Hamming Encoder and Decoder

Hamming Encoder

module hamming_encoder(clk,d,c);

input clk;
input [4:1] d;
output reg [7:1] c;
always @ (posedge clk)

begin
c[7]=d[4];
c[6]=d[3];
c[5]=d[2];
c[4]=d[2]^d[3]^d[4];
c[3]=d[1];
c[2]=d[1]^d[3]^d[4];
c[1]=d[1]^d[2]^d[4];
end
endmodule 

module encoder_test;
reg clk;
reg [4:1] d;
wire [7:1] c;

Test Bench

hamming_encoder encoder_test(clk,d,c);

initial
begin
forever
begin
clk=1;
#50 clk=0;
#50 clk=1;
end
end
initial
begin
d=4'b0000;
#100 d=4'b0001;
#100 d=4'b0010;
#100 d=4'b0011;
#100 d=4'b0100;
#100 d=4'b0101;
#100 d=4'b0110;
#100 d=4'b0111;
#100 d=4'b1000;
#100 d=4'b1001;
#100 d=4'b1010;
#100 d=4'b1011;
#100 d=4'b1100;
#100 d=4'b1101;
#100 d=4'b1110;
#100 d=4'b1111;
end
initial
begin
$monitor($time,"clk=%b,d=%b,c=%b",clk,d,c);
end
endmodule 

RTL Viewer

 

RTL Simulation

 

 

Hamming Decoder

 

module hamming_decoder(c,clk,s,c2,d );
input clk;
input [1:7] c;
output reg[1:3]s;
output reg[1:7]c2;
output reg[1:4]d;
always@(posedge clk)
begin
s[1] = c[1]^c[2];
s[2] = c[1]^c[3];
s[3] = c[1]^c[5]^c[6];
c2=c;
if(s)
c2[s-1]=~c[s-1];
end
always@(c2)
begin
d[1]=c2[3];
d[2]=c2[5];
d[3]=c2[6];
d[4]=c2[7];
end
endmodule

Test Bench

module decoder_test;
reg clk;
reg [1:7] c;
wire [1:3]s;
wire [1:7]c2;
wire [1:4]d;

hamming_decoder decoder_test(c,clk,s,c2,d);
initial
begin
forever
begin
clk=1;
#50 clk=0;
#50 clk=1;
end
end
initial
begin
c=7'b0000000;
#100 c=7'b1000111;
#100 c=7'b0011001;
#100 c=7'b0011110;
#100 c=7'b0101010;
#100 c=7'b0101101;
#100 c=7'b0110011;
#100 c=7'b0110100;
#100 c=7'b1001011;
#100 c=7'b1001100;
#100 c=7'b1010010;
#100 c=7'b1010101;
#100 c=7'b1100001;
#100 c=7'b1100110;
#100 c=7'b1111000;
#100 c=7'b1111111;
end
initial
begin
$monitor($time,"c=%b,clk=%b,s=%b,c2=%b,d=%b",c,clk,s,c2,d);
end
endmodule

RTL Viewer

 

 RTL Simulation