Verilog code for DOWN Counter

module down_counter(out,clk,reset);

input clk, reset;
output [3:0] out;
reg [3:0] out;
always @(posedge clk or posedge reset)

begin
if (reset)
out <= 4'd0 ;
else
out <= out - 1;
end
endmodule

Test Bench

module test_bench;

reg clk, reset;
wire [3:0] out;

down_counter test_bench(out,clk,reset);

initial
begin
forever
begin
clk=1;
#50 clk=0;
#50 clk=1;
end
end
initial
begin
reset=1;
#100 reset=0;
#1700 ;
end
initial
begin
$monitor($time,"clk=%b,reset=%b,out=%b",clk,reset,out);
end
endmodule

RTL Viewer

RTL Simulation