Verilog code for Ripple Carry Counter

D Flip-Flop

module d_ff(q,d,clk,reset);
input d,clk,reset;
output q;
reg q;

always@(negedge clk or posedge reset)
if (reset)
q <= 0;
else
q <= d;
endmodule

T Flip-Flop

 module t_ff(q,clk,reset);
input clk,reset;
output q;

wire d;
d_ff d_ff_1(q,d,clk,reset);
not(d,q);
endmodule

Ripple Carry Counter

module ripple_counter(q,clock,reset);
input clock,reset;
output [3:0]q;
t_ff t_ff_1 (q[0],clock,reset);
t_ff t_ff_2 (q[1],q[0],reset);
t_ff t_ff_3 (q[2],q[1],reset);
t_ff t_ff_4 (q[3],q[2],reset);

endmodule

Test Bench

module ripple_counter_test;
reg clk,reset;
wire [3:0]q;

ripple_counter  ripple_counter_test(q,clk,reset);

initial
clk = 1'b0;
always
#5 clk = ~ clk;
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish;
end
initial
begin
$monitor($time,"clk=%d,q=%d,reset=%d",clk,q,reset);
end
endmodule

RTL Viewer

RTL Simulation