VHDL Code For AND gate

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and_1 IS
PORT (A,B : IN STD_LOGIC;
        C : OUT STD_LOGIC);
          END and_1;
          architecture fun of and_1 is
          begin
          C<=A AND B;
          END FUN;

Test Bench

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
END TEST;
ARCHITECTURE FUN OF TEST IS
SIGNAL A,B : STD_LOGIC;
SIGNAL   C : STD_LOGIC;
BEGIN
UUT : ENTITY WORK.and_1 port map (A,B,C);
TEST : PROCESS
BEGIN
A<='0';
B<='0';
WAIT FOR 100 PS;
A<='0';
B<='1';
WAIT FOR 100 PS;
A<='1';
B<='0';
WAIT FOR 100 PS;
A<='1';
B<='1';
WAIT FOR 100 PS;
end process TEST;
end;
 

--Method 1:-when else --

library ieee;
use ieee.std_logic_1164.all;

entity and_1 is
port (a,b : in std_logic;
            c : out std_logic);
          end and_1;
          architecture beh of and_1 is
          begin
          c<='0' when (a='0' and b='0')else
                '0' when (a='1' and b='0')else
                '0' when (a='0' and b='1')else
                '1' when (a='1' and b='1');
          end beh;

--Method 2:-if else --

LIBRARY IEEE;
USE IEEE.STD_logic_1164.ALL;
ENTITY and_1 is
port (a,b: in std_logic;
c : out std_logic);
end and_1;
architecture beh of and_1 is
begin
ab :process(a,b)
begin
if (a='0' AND b='0') then
c<='0';
elsif (a='1' AND b='0') then
c<='0';
elsif (a='0' AND b='1') then
c<='0';
else
c<='1';
end if;
end process ab;
end beh;

--Method 3:-for loop --

LIBRARY IEEE;
USE IEEE.STD_logic_1164.ALL;
entity and_1 is
generic( n : natural := 2);
port(x : in std_logic_vector(1 to n);
     z : out std_logic);
end and_1;
architecture Behavioral of and_1 is
begin
    process(x)
    variable temp : std_logic;
    begin
    temp := '1';
    for i in 1 to n loop
        temp := temp and x(i);
    end loop;
z <= temp;
end process;
end Behavioral; 

----For Method 1,2 and 3 Test Bench----

library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture fun of test is
--generic( n : natural := 2);
signal x : std_logic_vector(1 to 2);
signal y : std_logic;
begin
uut:entity work.and_1 port map(x,y);
test :process
begin
x<="00";
wait for 100 ps;

x<="01";
wait for 100 ps;

x<="10";
wait for 100 ps;

x<="11";
wait for 100 ps;
end process test;
end;