Verilog code for 4-Bit Full Adder

Half-Adder

module halfadder_gate (s,c,a,b);
input  a,b;
output s,c;

xor(s,a,b);
and(c,a,b);

endmodule

Full-Adder

module full_adder(s,c,a,b,cin);
input a,b,cin;
output s,c;
wire i1,i2,i3;

halfadder_gate hf1 (i1,i2,a,b);
halfadder_gate hf2 (s,i3,i1,cin);
or (c,i2,i3);
endmodule

4-Bit Full-Adder

module fulladder_4bit(s,c,a,b,cin);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]s;
output c;
wire c0,c1,c2;

full_adder fa0(s[0],c0,a[0],b[0],cin);
full_adder fa1(s[1],c1,a[1],b[1],c0);
full_adder fa2(s[2],c2,a[2],b[2],c1);
full_adder fa3(s[3],c,a[3],b[3],c2);
endmodule

Test Bench

module test_bench;
reg[3:0]a;
reg[3:0]b;
reg cin;

wire c;
wire [3:0]s;

fulladder_4bit full_adder1(s,c,a,b,cin);
begin
#0 a=4'd0;b=4'd0;cin=1'b0;
#5 a=4'd5;b=4'd6;
#5 a=4'd8;b=4'd8;
#5 a=4'd7;b=4'd8;
#5 a=4'd12;b=4'd15;cin=1'b1;
end
initial
begin
$monitor($time,"a=%b,b=%b,cin=%b,s=%b,c=%b",a,b,s,c,cin);
end
endmodule

Full Adder using Half Adder RTL Viewer

 

4-Bit Full Adder RTL Viewer

 

 4-Bit Full Adder RTL Simulation