Verilog code for NOR gate

Gate Level Modeling

module nor_gate(c,a,b);
input a,b;
output c;
nor (c,a,b);
endmodule

Data Flow Modeling

module nor_data(c,a,b);
input a,b;
output c;
assign c=~(a|b);
endmodule

Behavioral Modeling

module nor_beh(c,a,b);
input a,b;
output c;
reg c;
always@(a,b)

begin
if (a==0 & b==0)
c=1;
else
c=0;
end
endmodule

Test Bench

module nor_test;
reg a,b;
wire c;
nor_gate nor_test(c,a,b);
initial
begin
#000 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
end
endmodule

Truth Table

Input A	Input B	Output c
0	0	1
0	1	0
1	0	0
1	1	0

RTL Viewer

 

 

RTL Simulation