Verilog code for D Flip-Flop

module d_ff_beh(D,CLK,RST,Q,Qbar);
output Q,Qbar;
input  D,CLK,RST;
reg  Q;
always @(posedge CLK)

begin // positive-edge triggered
if (!RST) // synchronous reset, active low
Q <= 1'b0;
else
Q <= D; // characteristic equation
end
assign Qbar = ~ Q ;
endmodule

Test Bench

module d_ff_test;
reg D,CLK;
wire Q,Qbar;

d_ff_beh d_ff_test(D,CLK,Q,Qbar);

initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
      D=0;
#100 D=1;
end
initial
begin
$monitor($time,"D=%B,CLK=%b,Q=%b,Qbar=%b",D,CLK,Q,Qbar);
end
endmodule

RTL Viewer

 

RTL Simulation