Verilog code for D-Latch Active High

module d_latch_act_high (q,qbar,d,enb); // active high enable
input d,enb;
output q,qbar;
reg q;
assign qbar = ~ q ;
always @( enb or d )
begin
if (enb) // input enb
q = d ;
end
endmodule

Test Bench

module d_latch_act_high_test;
reg d,enb;
wire q,qbar;

d_latch_act_high d_latch_act_high_test(q,qbar,d,enb);

initial
begin
#000 enb=1;d=0;
#100 enb=0;d=0;
#100 enb=0;d=1;
#100 enb=1;d=1;
end
initial
begin
$monitor($time,"d=%B,enb=%b,q=%b,qbar=%b",d,enb,q,qbar);
end
endmodule

RTL Viewer

RTL Simulation