Verilog code for Full-Adder

Gate Level Modeling

module fulladder_gate(s,c,a,b,cin);
input a,b,cin;
output s,c;
wire i1,i2,i3;
xor (i1,a,b);
and (i2,a,b);
xor (s,i1,cin);
and (i3,i1,cin);
or (c,i2,i3);
endmodule

Data Flow Modeling

module fulladder_data(s,c,a,b,cin);
input a,b,cin;
output s,c;
wire i1,i2,i3;
assign s=i1^cin;
assign i2=a&b;
assign i1=a^b;
assign i3=cin&i1;
assign c=i2|i3;
endmodule

Behavioral Modeling

module fulladder_beh(s,c,a,b,cin);
input a,b,cin;
output s,c;
reg s,c;
always@(a,b,cin)

begin
if (a==b)
begin
s=cin;
c=b;
end
else
begin
s=~cin;
c=cin;
end
end
endmodule

Test Bench

module fulladder_test;
reg a,b,cin;
wire s,c;
fulladder_gate fulladder_test(s,c,a,b,cin);
initial
begin
#000 a=0; b=0; cin =0;
#100 a=0; b=0; cin =1;
#100 a=0; b=1; cin =0;
#100 a=0; b=1; cin =1;
#100 a=1; b=0; cin =0;
#100 a=1; b=0; cin =1;
#100 a=1; b=1; cin =0;
#100 a=1; b=1; cin =1;
end
initial
begin
$monitor($time,"a=%b,b=%b,cin=%b,s=%b,c=%b",a,b,s,c,cin);
end
endmodule

RTL Viewer

Gate Level Modeling

Data flow Modeling

 

Behavioral Modeling

 

RTL Simulation