Verilog code for Half-Adder

Gate Level Modeling

module halfadder_gate (s,c,a,b);
input  a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule

Data Flow Modeling

module halfadder_data (s,c,a,b);
input  a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Behavioral Modeling

module halfadder_beh(s,c,a,b);
input a,b;
output s,c;
reg s,c;
always@(a,b)

begin
if (a==b)
begin
s=0;
c=b;
end
else
begin
s=1;
c=0;
end
end
endmodule

Test Bench

module halfadder_test;
reg a,b;
wire s,c;

halfadder_gate halfadder_test(s,c,a,b);
initial

begin
#000 a=0; b=0;
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,s=%b,c=%b",a,b,s,c);
end
endmodule

RTL Viewers

Gate Level Modeling

Data Flow Modeling

 

Behavioral Modeling

 

RTL Simulation