Verilog code for XOR gate

Gate Level Modeling

module xor_gate(c,a,b);
input a,b;
output c;
xor (c,a,b);
endmodule

Data Flow Modeling

module xor_data(c,a,b);
input a,b;
output c;
assign c=(a^b);
endmodule

Behavioral Modeling

module xor_beh(c,a,b);
input a,b;
output c;
reg c;
always@(a,b)

begin
if (a==0 & b==0)
c=0;
else if (a==1 & b==1)
c=0;
else
c=1;
end
endmodule

Test Bench

module xor_test;
reg a,b;
wire c;
xor_gate  xor_test(c,a,b);
initial
begin
#000 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
end
endmodule

Truth Table

Input A	Input B	Output c
0	0	0
0	1	1
1	0	1
1	1	0

RTL Viewer

RTL Simulation