Verilog code for JK Flip-Flop

module jk_ff_beh(J,K,CLK,RST,Q,Qbar);
output Q,Qbar;
input  J,K,CLK,RST;
reg  Q;
always @(posedge CLK)

begin // positive-edge triggered
if (!RST) // synchronous reset, active low
Q <= 1'b0;
else
Q <= (J & ~Q)|(~K & Q); // characteristic equation
end
assign Qbar = ~ Q ;
endmodule

Test Bench

module jk_ff_test;
reg J,K,CLK;
wire Q,Qbar;

jk_ff_beh jk_ff_test(J,K,CLK,Q,Qbar);

initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
#000 J=0;K=1;
#100 J=0;K=0;
#100 J=1;K=0;
#100 J=1;K=1;
#100 J=1;K=1;
#100 J=1;K=1;
end
initial
begin
$monitor($time,"J=%b,K=%b,CLK=%b,Q=%b,Qbar=%b",J,K,CLK,Q,Qbar);
end
endmodule

RTL Viewer

RTL Simulation