Verilog code for AND gate

Gate Level Modeling

module and_gate(c,a,b);
input a,b;
output c;
and (c,a,b);
endmodule

Data Flow Modeling

module and_data(c,a,b);
input a,b;
output c;
assign c = a & b;
endmodule

Behavioral Modeling

module and_beh(c,a,b);
input a,b;
output c;
reg c;
always@(a,b)

begin
if (a==0|b==0)
c=0;
else if(a==0|b==1)
c=0;
else if(a==1|b==0)
c=0;
else
c=1;
end
endmodule

Test Bench

module and_test;
reg a,b;
wire c;
and_gate  and_test(c,a,b);
initial
begin
#000 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
end
endmodule

Truth Table

Input A	Input B	Output c
0	0	0
0	1	0
1	0	0
1	1	1

RTL Viewer

 

 

RTL Simulation