Verilog code for T Flip-Flop

module t_ff_beh(T,CLK,RST,Q,Qbar);
output Q,Qbar;
input  T,CLK,RST;
reg  Q;
always @(posedge CLK)

begin // positive-edge triggered
if (!RST) // synchronous reset, active low
Q <= 1'b0;
else
Q <= T^Q;
//Q <= (~T&Q)|(T&~Q); // characteristic equation
end
assign Qbar = ~ Q ;
endmodule

Test Bench

module t_ff_test;
reg T,CLK;
wire Q,Qbar;

t_ff_beh t_ff_test(T,CLK,Q,Qbar);

initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
     T=0;
#100 T=1;
end
initial
begin
$monitor($time,"T=%B,CLK=%b,Q=%b,Qbar=%b",T,CLK,Q,Qbar);
end
endmodule

RTL Viewer

 

RTL Simulation