Verilog code for OR gate

Gate Level Modeling

module or_gate(c,a,b);
input a,b;
output c;
or (c,a,b);
endmodule

Data Flow Modeling

module or_data(c,a,b);
input a,b;
output c;
assign c=a|b;
endmodule

Behavioral Modeling

module or_beh(c,a,b);
input a,b;
output c;
reg c;
always@(a,b);

initial

begin
if (a==0|b==0)
c=0;
else if(a==0|b==1)
c=0;
else if(a==1|b==0)
c=0;
else
c=1;
end
endmodule

Test Bench

module or_test;
reg a,b;
wire c;
or_gate  or_test(c,a,b);
initial
begin
#000 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
end
endmodule

Truth Table

Input A	Input B	Output c
0	0	0
0	1	1
1	0	1
1	1	1

RTL Viewer

 

RTL Simulation