Verilog code for 4 to 2 line Encoder

module encoder_4_2(a,b,c,d,x,y);
output x,y;
input a,b,c,d;
assign x = b | d;
assign y = c | d;
endmodule

Test Bench

module encoder_4_2_test;
reg a,b,c,d;
wire x,y;

encoder_4_2 encoder_4_2_test(a,b,c,d,x,y);
initial

begin
#000 a=0; b=0;c=0;d=1;
#100 a=0; b=0;c=1;d=0;
#100 a=0; b=1;c=0;d=0;
#100 a=1; b=0;c=0;d=0;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b,d=%b,x=%b,y=%b",a,b,c,d,x,y);
end
endmodule

RTL Viewer

 

RTL Simulation