Verilog code for D-Latch Active Low

module d_latch_act_low(q,qbar,d,enb); // active low enable
input d,enb;
output q,qbar;
reg q;
assign qbar = ~ q ;
always @(enb or d)
begin
if (!enb) // if input !enb =0 then it take the value enb 1 bcz the active low enable
q = d ;
end
endmodule

Test Bench

module d_latch_act_low_test;
reg d,enb;
wire q,qbar;

d_latch_act_low d_latch_act_low_test(q,qbar,d,enb);

initial
begin
#000 enb=0;d=1;
#100 enb=0;d=0;
#100 enb=1;d=0;
#100 enb=1;d=1;
end
initial
begin
$monitor($time,"d=%B,enb=%b,q=%b,qbar=%b",d,enb,q,qbar);
end
endmodule

RTL Viewer

 

RTL Simulation