Verilog code for 4:1 MUX

Gate Level Modeling

module mux_gate(a,b,c,d,select0,select1,y);
input a,b,c,d,select0,select1;
output y;
wire i1,i2,i3,i4,i5,i6;
not (i1,select0);
not (i2,select1);
and (i3,i1,i2,a);
and (i4,i1,select1,b);
and (i5,select0,i2,c);
and (i6,select0,select1,d);
or (y,i3,i4,i5,i6);
endmodule

Data Flow Modeling

module mux_data(a,b,c,d,select0,select1,y);
input a,b,c,d,select0,select1;
output y;
wire i1,i2,i3,i4,i5,i6;
assign i1=~select0;
assign i2=~select1;
assign i3=i1&i2&a;
assign i4=i1&select1&b;
assign i5=select0&i2&c;
assign i6=select0&select1&d;
assign y=i3|i4|i5|i6;
endmodule

Behavioral Modeling

module  mux_beh(a,b,c,d,select0,select1,y);
input a,b,c,d,select0,select1;
output y;
reg  y;
always @ (a or b or c or d or select0 or select1)

begin
if (select0 == 0 & select1 ==0)
y = a;
else if (select0 == 0 & select1 ==1)
y = b;
else if (select0 == 1 & select1 ==0)
y = c;
else
begin
y = d;
end
end
endmodule

Test Bench

module mux_test;

reg a,b,c,d;
reg select0,select1;
wire y;

mux_gate mux_test(a,b,c,d,select0,select1,y);

initial
begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
d = 1'b0;
select0= 1'b0;
select1= 1'b0;
#64 $stop;
end   
always  #32 select0 = ~select0;
always  #16 select1 = ~select1;
always  #8 a = ~a;
always  #4 b = ~b;
always  #2 c = ~c;
always  #1 d = ~d;
initial
begin
$monitor($time,"a=%b,b=%b,c=%b,d=%b,select0=%b,select1=%b,y=%b",a,b,c,d,select0,select1,y);
end
endmodule

RTL Viewer

Gate Level Modeling

Data flow Modeling

 Behavioral Modeling

  

RTL Simulation