Verilog code for NOT gate

Gate Level Modeling

module not_gate(c,a);
input a;
output c;
not (c,a);
endmodule

Data Flow Modeling

module not_data(c,a);

input a;

output c;

assign c=~a;

endmodule

Behavioral Modeling

module not_beh(c,a);
input a;
output c;
reg c;
always@(a)
begin
if (a==0)
c=1;
else
c=0;
end
endmodule

Test Bench

module not_test;
reg a;
wire c;
not_gate  not_test(c,a);
initial
begin
#000 a=0;
#100 a=1;
end
initial
begin
$monitor($time,"a=%b,c=%b",a,c);
end
endmodule

Truth Table

Input A	Output c
0	1
1	0

RTL Viewer

 

RTL Simulation