Verilog code for 2:1 MUX

Gate Level Modeling

module mux_gate(a,b,select,y);
input a,b,select;
output y;
wire i1,i2,i3;
and (i2,i1,a);
and (i3,b,select);
not (i1,select);
or (y,i2,i3);
endmodule

Data Flow Modeling

module mux_data(a,b,select,y);
input a,b,select;
output y ;
wire i1,i2,i3;
assign i2=i1&a;
assign i3=b&select;
assign i1=~select;
assign y=i2|i3;
endmodule

Behavioral Modeling

module  mux_beh(a,b,select,y);
input a,b,select;
output y;
reg  y;
always @ (select, a , b)
begin
if (select == 0)
begin
y = a;
end
else
begin
y = b ;
end
end
endmodule 

Test Bench

module mux_test;
reg a,b,select;
wire y ;
mux_gate mux_test(a,b,select,y);      
initial
begin
select=0;a=0;b=0;
#100 select=0;a=0;b=1;
#100 select=0;a=1;b=0;
#100 select=0;a=1;b=1;
#100 select=1;a=0;b=0;
#100 select=1;a=0;b=1;
#100 select=1;a=1;b=0;
#100 select=1;a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,select=%b,y=%b",a,b,select,y);
end
endmodule

RTL Viewer

Gate Level Modeling

Data flow Modeling

Behavioral Modeling

 

RTL Simulation