Verilog code for 1:2 DEMUX

input Din,E,S0;
output Y0,Y1;

assign Y0 = (E & Din &(~S0));
assign Y1 = (E & Din & S0);
endmodule

Test Bench

module  demux1_2_test;

reg Din,E,S0;
wire Y0,Y1;

demux1_2  demux1_2_test(Din,E,S0,Y0,Y1);
initial
begin
#000 E=1'b0;Din=1'bX;S0=1'bX;
#100 E=1'b1;Din=1'b0;S0=1'b0;
#100 E=1'b1;Din=1'b1;S0=1'b0;
#100 E=1'b1;Din=1'b0;S0=1'b1;
#100 E=1'b1;Din=1'b1;S0=1'b1;
end
initial
begin
$monitor($time,"Din=%b,E=%b,S0=%b,Y0=%b,Y1=%b,",Din,E,S0,Y0,Y1);
end
endmodule

RTL Viewer

 

RTL Simulation